1. Field of the Invention
The invention herein relates to the formation of an integrated circuit including a capacitor. More specifically, this invention relates to the formation of a metal-insulator-metal capacitor in an integrated circuit.
2. Description of the Related Art
As integrated circuit (IC) complexity increases, the number of interconnections used in an IC increases accordingly. IC fabrication methods providing layouts multiple metal layer layouts have become popular techniques for accommodating increased number of interconnections in such ICs. Because highly-integrated ICs face difficulties meet the requisite yield and interconnect reliability requirements, newer methods and structures have been developed and applied in the semiconductor fabrication process. Two recently-developed fabrication techniques include the single damascene process and the dual damascene process. Single damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal, for example, copper, to form the conductive lines. Dual damascene is a multi-level interconnection process in which conductive via openings are formed in addition to forming the grooves of single damascene. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Because a dual damascene structure satisfies the requirement of low resistance and high electromigration, it has been widely used in deep sub-micron VLSI fabrication processes for obtaining an efficient and reliable interconnections. In fabricating very and ultra large scale integration (VLSI and ULSI) circuits with the copper dual damascene process, insulating or dielectric materials are patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal, and serve to interconnect the active and/or passive elements of the integrated circuit. However, dual damascene processes using copper metal fill can make device fabrication a daunting task. Copper is a known fast-diffuser and can act to “poison” a device, creating a failure, once it gets into the active area (i.e., source/drain/gate region of the transistor). This has required the development of new and advanced diffusion barriers to eliminate that threat, as well as different fab layouts to isolate the copper production part of the line from the rest of manufacturing. Metal-insulator-metal (MiM) capacitors are generally used in high-density integrated circuits in a variety of applications. For example, metal-electrode capacitors are widely used in mixed-signal/RF integrated circuits because of their better linearity and higher Q (due to lower electrode resistance) relative to other IC capacitor configurations. Metal-insulator-metal (MiM) capacitors have been commercially available in the standard CMOS mixed-signal process with aluminum interconnects, by adding a few additional steps to the traditional process flow. Present MiM fabrication techniques in dual damascene processes typically involve additional fabrication steps in which extra barrier and dielectric layers needed to form such devices tend to complicate an already difficult and expensive process. What is needed, then, is a MiM capacitor which can be reliably fabricated with fewer process steps using standard materials, preferably eliminating the additional fabrication steps typically associated with creating such devices.